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1 for more information www.linear.com/lt6023 typical application features description dual micropower , 1.4v/s precision rail-to-rail output amplifier the lt ? 6023 is a low power , enhanced slew rate , precision operational amplifier. the proprietary circuit topology of this amplifier gives excellent slew rate at low quiescent power dissipation without compromising precision or settling time. in addition, proprietary input stage circuitry allows the input impedance to remain high during input voltage steps as large as 5v. the combination of preci- sion specs along with fast settling makes this part ideal for mux applications. the low quiescent current of the lt6023 along with its ability to operate on supplies as low as 3v make it useful in portable systems. the lt6023-1 features a shutdown mode which reduces the typical supply current to 800na. the lt6023 is available in the small 8-lead dfn and 8-lead msop packages. the lt6023-1 is available in a 10-lead dfn package. 13.6v input range mux buffer mux buffer response, 12v step applications n precision signal processing n dac amplifer n multiplexed adc applications n low power portable systems n low power wireless sensor networks l, lt , lt c , lt m , linear technology, smartmesh and the linear logo are registered trademarks and softspan is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. patent pending. n excellent slew rate to power ratio n slew rate: 1.4v/s n maximum supply current: 20a/amplifer n maximum offset voltage: 30v n high dynamic input impedance n fast recovery from shutdown n maximum input bias current: 3na n no output phase inversion n gain bandwidth product: 40khz n wide specifed supply range: 3v to 30v n operating temperature range: C40c to 125c n rail-to-rail outputs n dfn and ms8 packages 60231 ta01a 1/2 ltc203 ?15v 15v in1 in2 s1 s2 gnd v + d1 d2 v ? 15v ?15v v in1 ?6v v in2 6v ? + 1/2 lt6023 5 0 2v/div 20s/div 60231 ta01b lt 6023 / lt 6023 -1 60231fa
2 for more information www.linear.com/lt6023 pin configuration absolute maximum ratings total supply voltage ( v + to v C ) ................................. 36 v differential input voltage ( within supplies ) ............... 36 v input voltage ( dgnd , en, + in , C in ) ( relative to v C ) ..................................................... 36 v input current (+ in , C in , dgnd , en ) ..................... 10 ma output short - circuit duration .......................... indefinite (note 1) top view dd package 8-lead (3mm 3mm) plastic dfn 5 6 7 8 4 3 2 1outa ?ina +ina v ? v + outb ?inb +inb 9 a b ja = 43c/w, jc = 5.5c/w exposed pad (pin 9) is connected to v C (pin 4) (pcb connection optional) top view 11 dd package 10-lead (3mm 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 v + outb ?inb +inb en outa ?ina +ina v ? dgnd a b ja = 43c/w, jc = 5.5c/w exposed pad (pin 11) is connected to v C (pin 4) (pcb connection optional) 1 2 3 4 outa ?ina +ina v ? 8 7 6 5 v + outb ?inb +inb top view ms8 package 8-lead plastic msop a b ja = 163c/w, jc = 40c/w order information lead free finish tape and reel part marking* package description temperature range lt6023idd#pbf lt6023idd#trpbf lgrs 8-lead (3mm 3mm) plastic dfn C40c to 85c lt6023hdd#pbf lt6023hdd#trpbf lgrs 8-lead (3mm 3mm) plastic dfn C40c to 125c lt6023idd-1#pbf lt6023idd-1#trpbf lgrv 10-lead (3mm 3mm) plastic dfn C40c to 85c lt6023hdd-1#pbf lt6023hdd-1#trpbf lgrv 10-lead (3mm 3mm) plastic dfn C40c to 125c lt6023ims8#pbf lt6023ims8#trpbf ltgrt 8-lead plastic msop C40c to 85c lt6023hms8#pbf lt6023hms8#trpbf ltgrt 8-lead plastic msop C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ operating and specified temperature range i - grade ................................................. C40 c to 85 c h - grade ............................................ .C40 c to 125 c junction temperature ........................................... 150 c storage temperature range .................. C65 c to 150 c lead temperature ( soldering , 10 sec ) ................... 300 c lt 6023 / lt 6023 -1 60231fa
3 for more information www.linear.com/lt6023 electrical characteristics symbol parameter conditions min typ max units v os input offset voltage dd packages l 20 70 160 v v ms8 package l 5 30 160 v v ?v osi ? temp input offset voltage drift (note 2) dd packages l C3.5 0.9 3.5 v/c ms8 package l C2.9 0.5 2.9 v/c ?v osi ? time long term input offset voltage stability 0.2 v/mo i b input bias current t a = C40 to 85c t a = C40 to 125c l l C3 C3 C10 0.1 3 3 10 na na na i os input offset current t a = C40 to 85c t a = C40 to 125c l l C1 C1 C2 0.1 1 1 2 na na na input noise voltage 0.1hz to 10hz 3 v p-p e n input noise voltage density f = 1hz f = 1khz 132 132 nv/hz nv/hz i n input noise current density f = 1khz 12.1 fa/hz c in input capacitance common mode differential mode 1.5 2.5 pf pf r in input resistance common mode differential mode 140 330 g m v icm common mode input range l v C + 1.2 v + C 1.4 v cmrr common mode rejection ratio v cm = C13.8v to 13.6v l 120 116 136 db db psrr supply rejection ratio v s = 3v to 30v l 120 110 140 db db a vol large-signal voltage gain r l = 10k, v out = 14v l 110 100 114 db db r l = 100k, v out = 14.5v l 126 116 134 db db v ol output swing low (v out C v C ) r l = 10k t a = C40 to 85c t a = C40 to 125c l l 180 300 380 430 mv mv mv v oh output swing high (v + C v out ) r l = 10k t a = C40 to 85c t a = C40 to 125c l l 115 140 165 190 mv mv mv i sc short- circuit current v out = 0v, sourcing t a = C40 to 85c t a = C40 to 125c l l 3 2.5 2 5.25 ma ma ma v out = 0v, sinking t a = C40 to 85c t a = C40 to 125c l l 6.5 4.5 4 15 ma ma ma the l denotes the specifications which apply over the specified temperature range, otherwise specifications are at t a = 25c, v s = 15v, v cm = v out = mid-supply, v dgnd = 0v, v en = 5v. dgnd and en specifications only apply to the lt6023-1. lt 6023 / lt 6023 -1 60231fa
4 for more information www.linear.com/lt6023 electrical characteristics symbol parameter conditions min typ max units sr slew rate a vcl = 1, 10v step t a = C40 to 85c t a = C40 to 125c l l 0.85 0.7 0.6 1.4 v/s v/s v/s a vcl = 1, 5v step t a = C40 to 85c t a = C40 to 125c l l 0.3 0.25 0.2 0.65 v/s v/s v/s gbw gain-bandwidth product f = 1khz l 29 40 khz minimum supply voltage guaranteed by psrr l 3 v i s supply current per amplifier t a = C40 to 85 c t a = C40 to 125c l l 18 20 28 40 a a a supply current in shutdown v en = 0.8v t a = C40 to 85c t a = C40 to 125c l l 0.8 3 3.2 3.6 a a a t s settling time (a v = 1) 0.1% 5v output step 0.01% 5v output step 0.0015% 5v output step 0.0015% 10v output step 40 60 124 132 s s s s t on enable time a v = 1 480 s v dgnd dgnd pin voltage range l v C v + C 3 v i dgnd dgnd pin current l C200 na i en en pin current l C200 na v enl en pin input low voltage relative to dgnd l 0.8 v v enh en pin input high voltage relative to dgnd l 1.7 v the l denotes the specifications which apply over the specified temperature range, otherwise specifications are at t a = 25c, v s = 15v, v cm = v out = mid-supply, v dgnd = 0v, v en = 5v. dgnd and en specifications only apply to the lt6023-1. lt 6023 / lt 6023 -1 60231fa
5 for more information www.linear.com/lt6023 electrical characteristics symbol parameter conditions min typ max units v os input offset voltage dd packages l 20 100 190 v v ms8 package l 5 45 175 v v ?v osi ? temp input offset voltage drift (note 2) dd packages l C3.5 0.9 3.5 v/c ms8 package l C2.9 0.5 2.9 v/c ?v osi ? time long term input offset voltage stability 0.2 v/mo i b input bias current 1 na i os input offset current 0.1 na input noise voltage 0.1hz to 10hz 3 v p-p e n input noise voltage density f = 1hz f = 1khz 132 132 nv/hz nv/hz i n input noise current density f = 1khz 12.1 fa/hz c in input capacitance common mode differential mode 1.5 2.5 pf pf r in input resistance common mode differential mode 140 400 g m v icm common mode input range l v C + 1.2 v + C 1.4 v cmrr common mode rejection ratio v cm = 1.2v to 1.6v 125 db psrr supply rejection ratio v s = 3v to 30v l 120 110 140 db db a vol large-signal voltage gain r l = 10k, v out = 0.5v to 2.5v l 98 95 108 db db r l = 100k, v out = 0.5v to 2.5v 136 db v ol output swing low (v out C v C ) r l = 10k t a = C40 to 85 c t a = C40 to 125c l l 60 100 150 170 mv mv mv v oh output swing high (v + C v out ) r l = 10k t a = C40 to 85c t a = C40 to 125c l l 60 80 90 100 mv mv mv i sc short- circuit current v out = 1.5v, sourcing t a = C40 to 85c t a = C40 to 125c l l 2.5 2.25 2 3.5 ma ma ma v out = 1.5v, sinking t a = C40 to 85c t a = C40 to 125 c l l 3.5 2 2 5 ma ma ma sr slew rate (note 3) a vcl = C1, 2v step 0.05 v/s gbw gain-bandwidth product f = 1khz 40 khz minimum supply voltage guaranteed by psrr l 3 v the l denotes the specifications which apply over the specified temperature range, otherwise specifications are at t a = 25c, v s = 3v, v cm = v out = mid-supply, v dgnd = 0v, v en = 3v. dgnd and en pin specifications only apply to the lt6023-1. lt 6023 / lt 6023 -1 60231fa
6 for more information www.linear.com/lt6023 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: guaranteed by design. note 3: the slew rate of the lt6023 increases with the size of the input step. at lower supplies, the input step size is limited by the input common mode range. this trend can be seen in the typical performance characteristics. electrical characteristics symbol parameter conditions min typ max units i s supply current per amplifier t a = C40 to 85c t a = C40 to 125c l l 15 20 25 35 a a a supply current in shutdown v en = 0.8v t a = C40 to 85c t a = C40 to 125c l l 0.2 1.1 1.5 3 a a a t s settling time (a v = C1) 0.1% 2.4v output step 0.01% 2.4v output step 0.0015% 2.4v output step 85 100 250 s s s t on enable time a v = 1 580 s v dgnd dgnd pin voltage range l v C v + C 3 v i dgnd dgnd pin current C75 na i en en pin current C75 na v enl en pin input low voltage relative to dgnd l 0.8 v v enh en pin input high voltage relative to dgnd l 1.7 v the l denotes the specifications which apply over the specified temperature range, otherwise specifications are at t a = 25c, v s = 3v, v cm = v out = mid-supply, v dgnd = 0v, v en = 3v. dgnd and en pin specifications only apply to the lt6023-1. lt 6023 / lt 6023 -1 60231fa
7 for more information www.linear.com/lt6023 typical performance characteristics offset voltage vs supply voltage offset voltage vs input common mode voltage t a = 25c, v s = 15v, r l = 100k, unless otherwise specified. total supply voltage (v) 0 offset voltage (v) 50 ?40 40 20 0 ?20 30 10 ?10 ?30 ?50 20 12 28 6023 g07 36 16 32 8 24 4 3 typical units input common mode voltage (v) ?15 offset voltage (v) 40 20 0 ?20 ?40 ?5 5 6023 g08 15 ?10 10 0 10 0 5 10 15 20 25 30 number of amplifiers ir re?ow ?4 ?3 ?1 0 1 3 4 5 0 20 offset voltage shift vs lead free 6023 g05 10 typical units temperature (c) ?50 ?25 0 25 50 75 40 60 80 100 120 140 160 number of amplifiers offset voltage drift typical distribution of input 100 125 ?160 ?120 ?80 ?40 0 40 80 120 6023 g03 20 dd packages 30 input offset voltage drift (v/c) 0 ?5 100 ?4 200 ?3 300 ?1 400 0 500 1 600 3 700 160 input offset voltage (v) vs temperature typical input offset voltage 6023 g06 4 800 5 number of amplifiers 0 offset voltage 10 typical distribution of input 20 6023 g01 30 40 2870 amplifiers dd8 and dd10 packages 50 input offset voltage (v) 60 ?80 70 ?60 80 ?40 90 ?20 number of amplifiers 0 offset voltage drift 20 typical distribution of input 40 6023 g04 60 210 amplifiers 80 ms8 package 0 80 amplifiers 200 input offset voltage shift (v) 400 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 600 800 1000 lt 6023 / lt 6023 -1 number of amplifiers 60231fa offset voltage ms8 package typical distribution of input 1386 amplifiers 6023 g02 input offset voltage (v) 215 amplifiers ms8 package input offset voltage drift (v/c) ?30 ?5 ?20 ?10 0 10
8 for more information www.linear.com/lt6023 typical performance characteristics slew rate vs temperature (5v step) slew rate vs temperature (10v step) t a = 25c, v s = 15v, r l = 100k, unless otherwise specified. slew rate vs input step temperature (c) ?50 slew rate (v/s) 1 0.75 0.5 0.25 0 25 75 6023 g15 125 ?25 0 100 50 falling edge rising edge input bias current vs temperature input bias current vs differential input voltage 0.1hz to 10hz voltage noise voltage noise density vs frequency large-signal transient response (5v step) maximum undistorted output amplitude vs frequency temperature (c) ?50 input bias current (na) 4 3 2 1 0 ?1 25 75 6023 g09 125 ?25 0 100 50 1v/div 1s/div 6023 g11 frequency (hz) voltage noise density (nv/ hz) 6023 g12 1000 100 10 0.01 0.1 1 1k 10k 10010 v s = 5v 2v/div 50s/div 6023 g14 10v step a v = 1 5v step temperature (c) ?50 slew rate (v/s) 2 1.5 1 0.5 0 25 75 6023 g16 125 ?25 0 100 50 falling edge rising edge input step size (v p?p ) 0 slew rate (v/s) 3.5 3 2.5 2 1.5 1 0.5 0 15 25 6023 g17 30 5 10 20 falling edge rising edge frequency (khz) maximum undistorted output voltage (v p?p ) 6023 g13 35 30 25 20 15 5 10 0 0.1 1 10 thd < 40dbc a v = 1 ?4 ?6 ?1 ?0.75 ?0.5 ?0.25 0 0.25 0.5 0.75 1 input bias current (a) 6023 g10 lt 6023 / lt 6023 -1 60231fa ib ? ib + differential input voltage (v) 6 4 2 0 ?2
9 for more information www.linear.com/lt6023 small-signal transient response overshoot vs capacitive load typical performance characteristics psrr vs frequency cmrr vs frequency open-loop gain and phase vs frequency open loop gain vs load output impedance vs frequency t a = 25c, v s = 15v, r l = 100k unless otherwise specified. load current (ma) open loop gain (db) 6023 g24 160 100 140 80 120 150 90 130 70 110 60 0.01 0.1 10 1 v out = 14.5v 2mv/div 50s/div 6023 g18 a v = 1 100pf 330pf capacitive load (pf) 0 overshoot (%) 35 25 15 30 20 10 5 0 600 6023 g19 1000 200 400 800 v s = 1.5v v s = 15v frequency (hz) power supply rejection ratio (db) 6023 g20 140 80 120 60 100 40 20 0 10m 100m 1 1k 100k10k 10010 +psrr ?psrr frequency (hz) common mode rejection ratio (db) 6023 g21 140 80 120 60 100 40 20 0 100m 1 1k 100k10k 10010 frequency (hz) open loop gain (db) open loop phase () 6023 g22 140 80 120 60 100 40 20 ?20 ?45 ?135 ?90 ?180 ?225 0 100m 1 1k 100k10k 10010 v s = 15v frequency (hz) output impedance () 6023 g25 10k 100 1 1k 10 0.1 0.01 10 100 1k 10k 1m 100k a v = 1 100k 1m ?12 ?9 ?6 ?3 0 3 gain (db) gain vs frequency 6023 g23 lt 6023 / lt 6023 -1 60231fa v s =15v c l =100p, a v =1 c l =330p, a v =1 c l =330p, a v =?1 frequency (hz) 100 1k 10k
10 for more information www.linear.com/lt6023 typical performance characteristics negative output overdrive recovery positive output overdrive recovery crosstalk vs frequency t a = 25c, v s = 15v, r l = 100k unless otherwise specified. supply current vs supply voltage shutdown supply current vs temperature start-up response enable/disable response output saturation voltage vs sink current (output low) output saturation voltage vs source current (output high) total supply voltage (v) suppy current per amplifier (a) 6023 g26 40 10 30 20 35 5 25 15 0 0 10 30 20 5 15 25 125c 85c 25c ?40c temperature (c) ?50 shutdown supply current (a) 2 1.5 1 0.5 0 25 75 6023 g27 125 ?25 0 100 50 v s = 15v v s = 1.5v 0v 0ma 0v 200s/div 6023 g28 v s = 10v a v = 1 v in = 1v v s 20v/div v out 2v/div i + 5ma/div 0v 0a 0v 500s/div 6023 g29 v en 5v/div v out 5v/div i + 40a/div load current (ma) output low saturation voltage (v) 6023 g30 1 0.1 0.01 0.1 1 10 t a = 125c t a = 85c t a = 25c t a = ?40c load current (ma) output high saturation voltage (v) 6023 g31 1 0.1 0.01 0.1 1 10 t a = 125c t a = 85c t a = 25c t a = ?40c frequency (hz) crosstalk (db) 6023 g32 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 10 1k100 10k 100k 1m 0v 2ms/div 6023 g33 a v = 100 input 200mv/div output 5v/div 0v 2ms/div 6023 g34 a v = 100 input 200mv/div output 5v/div lt 6023 / lt 6023 -1 60231fa
11 for more information www.linear.com/lt6023 pin functions out: amplifier output. Cin: inverting input of the amplifier. +in: noninverting input of the amplifier. v C : negative power supply. a bypass capacitor should be used between supply pins and ground. additional bypass capacitance may be used between the power supply pins. dgnd ( lt 6023 -1 only ): reference for en pin . it is normally tied to ground. dgnd must be in the range from v C to v + C3v. if grounded, v + must be 3 v. the en pin threshold is specified with respect to the dgnd pin. dgnd cannot be floated. en (lt6023-1 only): enable input. this pin must be connected high, normally to v + , for the amplifiers to be functional. en is active high with the threshold approxi- mately two diodes above dgnd. en cannot be floated. the shutdown threshold voltage is specified with respect to the voltage on the dgnd pin. v + : positive power supply. a bypass capacitor should be used between supply pins and ground. additional bypass capacitance may be used between the power supply pins. simplified schematic 60231 ss +in v + ?in 6k 6k out en 2m 2m lt6023-1 only dgnd v ? load class ab drive lt 6023 / lt 6023 -1 60231fa
12 for more information www.linear.com/lt6023 applications information figure 1. settling time is essentially flat will lower the slew rate to 0.02v/s. note that for these smaller inputs the lt6023 slew rate approaches the slew rate more common in traditional micropower amplifiers. input bias current the design of the input stage of the lt6023 is more so- phisticated than that shown in the simplified schematic. it uses both npn and pnp input differential amplifiers to sense the input differential voltage. as a result the speci- fied input bias current may flow in or out of the input pins. multiplexer applications/high dynamic input impedance the lt6023 has features which make it desirable for multiplexer applications, such as the application featured on the front page of this data sheet. when the channels of the multiplexer are cycled, the output of the multiplexer can produce large voltage transitions. normally, bipolar amplifiers have back-to-back diodes between the inputs, which will turn on when the input transient voltage exceeds 0.7v, causing a large transient current to be conducted from the amplifier output stage back into the input driving circuitry. the driving circuitry then needs to absorb this current and settle before the amplifier can settle. the lt6023 uses 5.5v zener diodes to protect its inputs which dramatically increases its input impedance with input steps as large as 5v. output step (v p-p ) 5 settling time (s) 200 150 100 50 0 20 60231 f01 25 10 15 a v = 1 0.01% 0.0015% preserving low power operation the proprietary circuitry used in the lt6023 provides an excellent combination of low power, low offset and en- hanced slew rate. normally an amplifier with higher supply current would be required to achieve this combination of slew rate and precision. special care must be taken to ensure that the low power operation is preserved. the choice of feedback resistor values impacts several op- amp parameters as noted in the feedback compo- nents section. it should also be noted that the output of the amplifier must drive this network. for example, in a gain of two with a total feedback resistance of 10k and an output voltage of 14v, the amplifiers output will need to supply 1.4ma of current. this current will ultimately come from a supply. the supply current of the lt6023 increases with large differential input voltages. normally, this does not impact the low power nature of the lt6023 because the ampli- fier is forcing the two inputs to be at the same potential. conditions which cause differential input voltage to appear should be avoided in order to preserve the low power dis- sipation of the lt6023. this includes but is not limited to : operation as a comparator, excessive loading on the output and overdriving the input. enhanced slew rate the lt6023 uses a proprietary input stage which provides an enhanced slew rate without sacrificing input precision specs such as input offset voltage , common mode rejection and noise. the unique input stage of the lt6023 allows the output to quickly slew to its final value when large signal input steps are applied. this enhanced slew characteristic allows the lt6023 to quickly settle the output to 0.0015% independent of input step size as shown in figure 1. typical micropower amplifiers cannot process large amplitude sig - nals with this speed. as shown in the typical performance curves , when the lt6023 is configured in unity gain and a 10v step is applied to the input the output will slew at 1.4v /s. in this same configuration, a 5v input step will slew the output at 0.65 v /s . furthermore , a 0.7 v input step lt 6023 / lt 6023 -1 60231fa
13 for more information www.linear.com/lt6023 applications information figure 2. some op amp configurations do not require rail-to-rail inputs to achieve rail-to-rail outputs r g v ref noninverting: a v = 1 + r f /r g inputs move by as much as v in , but the output moves more input may not have to be rail-to-rail noninverting: a v = 1 inputs move by as much as output input must be rail-to-rail for overall circuit rail-to-rail performance inverting: a v = ?r f /r g op amp inputs do not move, but are fixed at dc bias point v ref input does not have to be rail-to-rail v in r f ? + v in v ref r f r g ? + v in 60231 f02 ? + accuracy is limited by the resistors shown to 0.2%. output referred, this error becomes 2.7mv. the 30v input offset voltage contribution, plus the additional error due to input bias current times the ~10k effective source impedance, contribute only negligibly to error. phase inversion the lt 6023 input stage is limited to operating between v C + 1.2 v and v + C 1.4 v . exceeding this common mode range will cause the open loop gain to drop significantly . for a unity gain amplifier, the output roughly tracks the input well beyond the specified input voltage range as shown in figure 4. figure 4. no phase inversion 0v5v/div ?20v ?10v 20v 10v 2ms/div 60231 f04 output input ?v cm limit +v cm limit v s = 15v a v = 1 figure 3. extreme inverting case: circuit operates properly with input voltage swing well outside op amp supply rails 1.5v ?1.5v 10k, 0.1% 100k, 0.1% v in 1.35v output swing 13.5v swings well outside supply rails ? + lt6023 60231 f03 achieving rail-to-rail operation without rail-to-rail inputs the lt6023 output is able to swing close to each power supply rail, but the input stage is limited to operating between v C + 1.2 v and v + C 1.4 v. for many inverting applications and noninverting gain applications, this is largely inconsequential. figure 2 shows the basic op amp configurations, what happens to the op amp inputs and whether or not the op amp must have rail-to-rail inputs. the circuit of figure 3 shows an extreme example of the inverting case. the input voltage at the 100k resistor can swing 13.5v and the lt6023 will output an inverted, divided-by-ten version of the input voltage. the output lt 6023 / lt 6023 -1 60231fa
14 for more information www.linear.com/lt6023 figure 5. increased ib beyond vicm 7 6 5 4 3 2 1 0 ?1 ?2 ?3 0 5 ?5?10?15 10 15 input common mode voltage (v) input bias current (a) 60231 f05 however the open loop gain is significantly reduced. while the output roughly tracks the input, the reduction in open loop gain degrades the accuracy of the lt6023 in this region. exceeding the input common mode range also causes a significant increase in input bias current as shown in figure 5. the output of the lt6023 is guaranteed over the specified temperature range not to phase invert as long as the input voltage does not exceed the supply voltage. preserving input precision preserving the input accuracy of the lt6023 requires that the application circuit and pc board layout do not introduce errors comparable to or greater than the offset of the amplifiers. temperature differentials across the input connections can generate thermocouple voltages of tens of microvolts so the connections of the input leads should be short, close together and away from heat dis- sipating components. air currents across the board can also generate temperature differentials. as is the case with all amplifiers , a change in load current changes the finite open loop gain. increased load current reduces the open loop gain as seen in the typical performance characteristics section. this results in a applications information change in input offset voltage . under large signal conditions with load currents of 1ma the effective change in input error is just tens of microvolts. in precision applications it is important to consider amplifier loading when selecting feedback resistor values as well as the loads on the device. feedback components care must be taken to ensure that the phase shift formed by the feedback resistors and the parasitic capacitance at the inverting input does not degrade stability. for example, in a gain of +2 configuration, with 1m feedback resistors and a poorly designed circuit board layout with parasitic capacitance of 10pf (amplifier + pc board) at the ampli- fiers inverting input will cause the amplifier to have poor phase margin due to a pole formed at 32khz. an additional capacitor of 10pf across the feedback resistor as shown in figure 6 will eliminate any ringing or oscillation. capacitive loads the lt6023 can drive capacitive loads up to 100pf in unity gain. the capacitive load driving capability increases as the amplifier is used in higher gain configurations. a small series resistance between the output and the load will further increase the amount of capacitance that the amplifier can drive. figure 6. stability with parasitic input capacitance 1m 1m 10pf c par v out v in 60231 f06 + ? lt6023 lt 6023 / lt 6023 -1 60231fa
15 for more information www.linear.com/lt6023 applications information figure 7. lt6023-1 enable pin control examples ?15 +15 off on ?14.2v ?13.3v dgnd high voltage split supplies to v + or en logic en 60231 f07 + ? lt6023-1 ?15 +15 off on 0.8v 1.7v dgnd high voltage split supplies to v + or en logic en + ? lt6023-1 +30 off on 0.8v 1.7v dgnd high voltage single supply to v + or en logic en + ? lt6023-1 +3v off on 0.8v 1.7v dgnd low voltage single supply to v + or en logic en + ? lt6023-1 ?1.5 +1.5 off on ?0.7v 0.2v dgnd low voltage split supplies to v + or en logic en + ? lt6023-1 shutdown operation (lt6023-1) the lt6023-1 shutdown function has been designed to be easily controlled from single supply logic or microcontollers . to enable the lt6023 -1 when v dgnd = 0 v the enable pin must be driven above 1.7v. conversely, to enter the low power shutdown mode the enable pin must be driven below 0.8v. in a 15v dual supply application where v dgnd = C15 v, the enable pin must be driven above ~ C13.3v to enable the lt6023-1. if the enable pin is driven below C14.2v the lt6023-1 enters the low power shutdown mode. note that to enable the lt6023-1 the enable pin voltage can range from C13.3v to 15v whereas to disable the lt6023-1 the enable pin can range from C15v to C14.2v. figure 7 shows examples of enable pin control. while in shutdown, the outputs of the lt6023-1 are high impedance. the lt 6023 -1 is typically capable of coming out of shutdown within 480s. this is useful in power sensitive applications where duty cycled operation is employed such as wireless mesh networks. in these applications the system is in low power mode the majority of the time, but then needs to wake up quickly and settle for an acquisition before being powered back down to save power. lt 6023 / lt 6023 -1 60231fa
16 for more information www.linear.com/lt6023 typical applications 60231 f02a v in v out ? + 1/2 lt6023 ? + 1/2 lt6023 680pf 10k 10k 4.7pf load 60231 f02b v in v out ? + 1/2 lt6023 ? + 1/2 lt6023 100 100 high open-loop gain composite amplifier parallel amplifiers achieves 93nv/hz noise, doubles output drive and lowers offset lt 6023 / lt 6023 -1 60231fa
17 for more information www.linear.com/lt6023 micropower reference divider/buffer typical applications 60231 f02c 12v ? + 1/2 lt6023 ? + 1/2 lt6023 r5 49.9 c5 0.1f c6 10f r6 49.9k r7 49.9 r2* 100k c3 0.1f r3* 100k c4 10f c2 1f c1 0.1f r1* 100k r4* 100k lt6656-4.096 in out gnd 4.096v 2.048v *lt5400-2 lt 6023 / lt 6023 -1 60231fa
18 for more information www.linear.com/lt6023 package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-1) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 1 4 8 5 pin 1 top mark (note 6) 0.200 ref 0.00 ? 0.05 (dd8) dfn 0509 rev c 0.25 0.05 2.38 0.05 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 1.65 0.05 (2 sides) 2.10 0.05 0.50 bsc 0.70 0.05 3.5 0.05 package outline 0.25 0.05 0.50 bsc dd package 8-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1698 rev c) lt 6023 / lt 6023 -1 60231fa
19 for more information www.linear.com/lt6023 package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dd) dfn rev c 0310 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.70 0.05 3.55 0.05 package outline 0.25 0.05 0.50 bsc dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev c) pin 1 notch r = 0.20 or 0.35 45 chamfer lt 6023 / lt 6023 -1 60231fa
20 for more information www.linear.com/lt6023 package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. msop (ms8) 0213 rev g 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 ? 0.38 (.009 ? .015) typ 0.1016 0.0508 (.004 .002) 0.86 (.034) ref 0.65 (.0256) bsc 0 ? 6 typ detail ?a? detail ?a? gauge plane 1 2 3 4 4.90 0.152 (.193 .006) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660 rev g) lt 6023 / lt 6023 -1 60231fa
21 for more information www.linear.com/lt6023 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 04/15 updated typical slew rate to be consistent throughout the data sheet corrected negative supply voltage on front page circuit corrected input bias current vs. differential input voltage graph 1, 4 1 8 lt 6023 / lt 6023 -1 60231fa
22 for more information www.linear.com/lt6023 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 ? linear technology corporation 2015 lt 0415 rev a ? printed in usa (408) 432-1900 fax : (408) 434-0507 www.linear.com/lt6023 related parts typical application part number description comments lt6004 2khz, 1a rrio op amp v os : 500v, gbw: 2khz, sr: 0.8v/ms, e n : 325nv/hz, i s : 1a LT1490A 200khz, 50a rrio op amp v os : 500v, gbw: 200khz, sr: 0.06v/s, e n : 50nv/hz, i s : 50a ltc6256 6.5mhz, 65a rrio op amp v os : 350v, gbw: 6.5mhz, sr: 1.8v/s, e n : 20nv/hz, i s : 65a lt6020 400khz, 100a, 5v/s op amp v os : 30v, gbw: 400khz, sr: 5v/s, e n : 46nv/hz, i s : 100a ltc2055 500khz, 150a zero-drift op amp v os : 3v, gbw: 500khz, sr: 0.5v/s, i s : 150a lt1783 1.2mhz, 230a over-the- top rrio op amp v os : 600v, gbw: 1.2mhz, sr: 0.4v/s, e n : 20nv/hz, i s : 230a lt1352 3mhz. 200v/s op amp v os : 600v, gbw: 3mhz, sr: 200v/s , e n : 14nv/hz, i s : 330a lt1492 5mhz, 3v/s op amp v os : 180v, gbw: 5mhz, sr: 3v/s, e n : 16.5nv/hz, i s : 550a ltc5800 smartmesh ? wireless sensor network i c wireless mesh networks lt5400 quad matched resistor network 0.01% matching 16-bit dac with 10v output swing 20v output step response improved load drive capability gain of 11 instrumentation amplifier 60231 ta03b v + v out v ? v in ? + lt6023 load 1k 2n3904 2n3906 60231 ta03d 5v/div 200s/div v out 60231 ta03c v out gnd ref v dd ltc2642 1f r fb inv 16-bit dac control logic ? + cs din clr sclk 16-bit data latch 16-bit shift register 0.1f 3.8v dc to 5.5v dc 0.1f 15v ?15v lt5400-2 100k matched resistor network ? + 1/2 lt6023 1/2 lt6023 v out power-on reset ltc6652-2.5 in out gnd 60231 ta03a v inm r1 to r4: for high dc cmrr use lt5400-3 v inp ? + 1/2 lt6023 ? + 1/2 lt6023 r1, 100k ?3db bw = 6khz r2, 10k v out r3, 10k r4, 100k lt 6023 / lt 6023 -1 60231fa

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